Memory devices are used in a variety of electronic systems including computers, cellular phones, pagers, personal digital assistants, avionic systems, automotive systems, industrial control systems, appliances, etc. Depending on the particular system configuration, the memory devices may be either non-volatile or volatile. A non-volatile memory device retains the data or instructions stored therein when the device is turned off or power is removed. A volatile memory device, on the other hand, does not retain the stored data or instructions when the device is turned off. Flash memory has become an important type of non-volatile memory because it is less expensive to manufacture and denser than most other types of memory devices. In addition, Flash memory is electrically erasable and has a life span of up to one million write cycles.
Memory systems such as flash memory are typically configured on a semiconductor chip such that high density memory arrays occupy a central portion of the chip and lower density control and logic circuitry are placed along peripheral portions of the chip. The high-density memory arrays are typically comprised of memory cells arranged in columns and rows. FIG. 1 is a schematic diagram illustrating a prior art memory array 10 in a NOR type circuit architecture. Memory array 10 comprises an array of memory cells 12 arranged in columns and rows, where each memory cell has a control gate terminal, a drain terminal, and a source terminal. Memory cells 20, 22, 24, and 26 form a column. Their drain terminals connect to a bit line BL1 and their source terminals connect to a source line SL. Likewise, memory cells 30, 32, 34, and 36 form a column wherein their drain terminals connect to bit line BL2 and their source terminals connect to source line SL. Memory cells 40, 42, 44, and 46 form a column in which their drain terminals connect to bit line BL3 and their source terminals connect to source line SL. Memory cells 50, 52, 54, and 56 form a column in which their drain terminals connect to bit line BL 4 and their source terminals connect to source line SL.
The gate terminals of memory cells 20, 30, 40, and 50 connect to a word line WL1. Likewise, the gate terminals of memory cells 22, 32, 42, and 52 connect to a word line WL2; the gate terminals of memory cells 24, 34, 44, and 54 connect to a word line WL3; and the gate terminals of memory cells 26, 36, 46, and 56 connect to a word line WL4.
A drawback with this type of memory array configuration is the amount of silicon area it consumes. One reason this type of memory array configuration consumes a large silicon area is that one drain contact is required for every two memory cells.
Accordingly, what is needed is a memory device and a cost-effective method for manufacturing a memory device that increases the density of the memory cells of the memory array.